1. Field of the Invention
The present invention relates to a hybrid MRAM architecture, and more particularly to a hybrid MRAM architecture capable of being used with a micro-controller unit (MCU) and a micro-processing unit (MPU).
2. Description of Related Art
At present, the static random access memory (SRAM), dynamic random access memory (DRAM) and flash memory (FLASH) are widely used in the industry. These different kinds of memories all have their respective disadvantages, such as follows:
A DRAM has to write the same information again within a specific period of time (i.e., the so-called information refresh operation) to maintain the contents of the information stored therein. Although without the requirement of the information refresh operation as in the DRAM, the SRAM has a storage density much lower than that of DRAM. Thus, the SRAMs are not suitable for the case where an application of high storage density is required. In addition, once the power is turned off, the information stored in the SRAM and DRAM will be lost and the information contents cannot be maintained. Nevertheless, in the same situation, the information stored in a flash memory will not be lost. It is, however, necessary for the flash memory to continue monitoring the cumulative number of operations in a block (wear out monitor). As such, not only the limitation of the access speed exists, but also the difficulty in designing the interface between the host and the memory increases dramatically. Therefore, the industry currently lacks a single memory capable of being applied to various different circumstances, as in the random access memory (RAM) and the read only memory (ROM) of the present computers. Therefore, if an appropriate memory is chosen to meet with the different requirements of different application circumstances, the processes for designing and manufacturing a system-on-chip (SOC) can be further simplified. The manufacturing cost of the SOC can be reduced, too.
Recently, a novel memory—MRAM has been developed, providing an alternative for the industry. The MRAM has not only the non-volatile characteristic of the FLASH but also a storage density comparable to that of the DRAM and an access speed close to that of the SRAM. Furthermore, the information written into and read out of the MRAM can be performed numbers of times without any limitation as in the DRAM and SRAM. Hence, the MRAM is expected to integrate all of the currently available memories such as FLASH, DRAM and SRAM so as to simplify the process for manufacturing the computer memory and reduce the manufacturing cost significantly. Consequently, the SOC systems can have only the central processing unit (CPU) and the MRAM memory in the future.
Nevertheless, the MRAM has two different kinds of architectures, namely, the one transistor-one magnetic tunnel junction per cell (1T1MTJ) architecture and the cross-point cell (XPC) architecture, as shown in FIGS. 1A and 1B respectively. As illustrated in FIG. 1A, in the 1T1MTJ architecture, each memory cell is connected to a transistor. Hence, the principle of both writing and reading operations of the 1T1MTJ architecture MRAM is similar to that of the DRAM; namely, the speed of both the writing and reading operations is compatible with that of the DRAM. However, because each of the memory cells is connected to a transistor, the storage density of the 1T1MTJ architecture MRAM cannot be increased, and thus, the storage capacity of the 1T1MTJ architecture MRAM is limited.
On the other hand, as illustrated in FIG. 1B, in the XPC architecture, a number of memory cells share a single transistor as opposed to the connection of each of the memory cells to one transistor. Thus, the speed of both the writing and reading operations of the XPC architecture MRAM is slower, as compared with that of the 1T1MTJ architecture MRAM. Even so, the storage density of the XPC architecture MRAM is higher than that of the 1T1MTJ architecture MRAM. Hence, the storage density of the memory, as a whole, can be significantly increased.
Accordingly, to replace all of the presently available memories with the MRAM, the industry requires an MRAM architecture having both the two different architectures and characteristics thereof integrated. Thus, the resulting single memory of MRAM can be used for various demands for memory applications as in the RAM and ROM.